While lithographically engineered charge traps can be used for single-electron transport, ‘accidental’ single-electron trapping behaviour can also occur, particularly in very small semiconductor devices. This can be a nuisance in some circumstances, but might also provide useful access to single-electron transistor (SET) effects in simple devices. Researchers at e-SI-Amp partner University of Southampton (UoS) and National Physical Laboratory (NPL) have studied the well-known Coulomb Blockade effect (the modification of electrical transport by single particle charging effects) in advanced Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). Single electron/hole appear in some voltage ranges, making it possible to use them as single electron transistors (SETs).

Coulomb Blockade in pMOS and nMOS single gate transistors at low temperature

There is a strong motivation in the semiconductor industry to explore new quantum technology applications while using the existing silicon manufacturing platform. Single electron tunneling devices are one of the most promising candidate for these applications, for instance for use in RF-mixers. While Si-based SETs have been demonstrated, the specialised device structure required is complicated and difficult to fabricate compared to standard schemes.

In this work, scientists at the University of Southampton observed Coulomb blockade effects in relatively simple, single-gate field effect devices at low temperatures (2 K). There is evidence for the presence of quantum dots in the subthreshold regimes of both p-type and n-type MOSFETs in the subthreshold regimes, suggesting that advanced CMOSFETs might also work as single electron transistors under these conditions.

The quantum dots are presumed to arise due to local variations of equivalent oxide thickness due to the remote surface roughness of Poly-Si grain boundaries. An additional observation of current peaks in the stability diagram, near the edge of Coulomb diamonds, may be associated with charge traps which may be related to the observed reliability issues in advanced CMOSFETs.

This research was published as open-access in the Semiconductor Science and Technology, a journal of the Institute of Physics (IOP).

Single carrier trapping and de-trapping in scaled silicon complementary metal-oxide-semiconductor field-effect transistors at low temperatures
Zuo Li, Muhammad Khaled Husain, Hiroyuki Yoshimoto, Kazuki Tani, Yoshitaka Sasago, Digh Hisamoto, Jonathan David Fletcher, Masaya Kataoka, Yoshishige Tsuchiya, Shinichi Saito
Semiconductor Science and Technology  32, 075001 (2017);doi: 10.1088/1361-6641/aa6910